1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to the arrangement and construction of an output circuit for a column sense amplifier and data output transistor.
2. Description of the Related Art
A typical example of the conventional semiconductor memory device is schematically constructed as follows. A large number of memory cells are arranged in a matrix form in a memory cell array. An address buffer, row decoder, column sense amplifier, column decoder and the like are provided adjacent to the memory cell array. Address data temporarily stored in the address buffer is supplied to the row decoder and column decoder. The row decoder and column decoder select one of the memory cells. That is, when the row decoder selects one of the rows of memory cells, memory cells connected to the selected row are activated. Data read out from the activated memory cells are supplied to the column sense amplifier via bit lines connected to the respective activated memory cells and amplified by the amplifier. One of the signals amplified by the column sense amplifier is selected by selecting one of the columns of the memory cell array by the column decoder. Data read out from the selected memory cell is supplied to an output circuit via data lines. The output circuit includes a main sense amplifier and an output control circuit. The output control circuit is used to control the conduction states of output transistors (a P-channel MOS transistor and an N-channel MOS transistor whose current paths are connected in series with each other between power sources V.sub.DD and V.sub.SS). The output control circuit causes to be output from a connection node between the output transistors under the control of output enable signal OE, and causes the output terminal to be set at a high impedance state.
In a case where the memory cell array is divided into a plurality of blocks, a row decoder, a column decoder and a column sense amplifier are provided for each of the memory cell array blocks. Further, an array selection circuit for selecting data read out from the memory cell array block is provided Data read out from the memory cell array block selected by the array selection circuit is supplied to the output circuit.
In the above semiconductor memory device, the output circuit is constructed as shown in FIG. 1. The source of output MOS transistor Qp is connected to V.sub.DD power source terminal 11 and V.sub.DD power source line 12 in the chip. A wiring between transistor Qp and V.sub.DD power source terminal 11 has inductance component L1 due to a bonding wire or the like. Inductance component L1 is shown surrounded by a dashed line to indicate that it is a parasitic element. The source of output MOS transistor Qn is connected to V.sub.SS power source (ground terminal) and V.sub.SS power source line 13 in the chip. A wiring between transistor Qn and V.sub.SS power source also has inductance component L2 due to a bonding wire or the like. Inductance component L2 is shown surrounded by a dashed line to indicate that it is a parasitic element. The drains of transistors Qp and Qn are connected to each other, and connected to output terminal 14 for outputting output signal Vout to the exterior. Output load capacitor Cl is connected between output terminal 14 and the V.sub.SS power source. Inductance component L3 also exists between output terminal 14 and output load capacitor C1. Inductance component L3 is shown surrounded by a dashed line to indicate that it is a parasitic element. The conduction state of transistor Qp is controlled by potential VGP supplied from inverter 16 provided at the output stage of output control circuit 15. Likewise, the conduction state of transistor Qn is controlled by potential VGN supplied from inverter 17 provided at the output stage of output control circuit 15. Further, internal circuit 18 is connected between V.sub.DD power source line 11 and V.sub.SS power source line 12.
If inductance components L1 to L3 exist as described above, the source potential (V.sub.SS ' potential in the chip) of N-channel MOS transistor Qn will significantly fluctuate as shown in FIG. 2A when N-channel MOS transistor Qn is turned on at a high speed to invert the potential of output terminal 14 from the high level to the low level (that is, discharge charges of output terminal 14). If such a large potential variation (noise) occurs, internal circuit 18 on the chip will be erroneously operated. In order to prevent the V.sub.SS ' potential in the chip from significantly fluctuating when the output is changed, gate driving potential VGN for N-channel MOS transistor Qn is generally changed at a small variation rate as shown in FIG. 2B and 5 ns or more time is assigned to change the output.
Likewise, in a case where the potential of output terminal 14 is inverted from the low level to the high level, gate driving potential VGP for P-channel MOS transistor Qp is smoothly changed in order to prevent the V.sub.DD ' potential in the chip from significantly fluctuating.
As described above, in order to prevent the erroneous operation due to the power source potential variation, the driving ability of inverters 16 and 17 of output control circuit 15 is suppressed to delay the output thereof in the prior art so as to smoothly change gate driving potentials VGN and VGP.
A data line has a parasitic capacitance of approx. 2 pF and it will take 5 ns or more for the column decoder to drive the data line. This is because the operation speed of the column sense amplifier is slow since it amplifies a small signal such as memory data, and it becomes necessary to drive a large capacitor. Further, in order to suppress variation in the power source potential in the chip when the output is changed, the operation of the output control circuit is delayed by approx. 5 ns. Therefore, the conventional semiconductor memory device is largely limited in reducing the access time, thus making it difficult to realize the high speed access.